FIG. 1 shows an existing bond pad structure commonly used in a package of an integrated circuit chip. The bond pad structure is formed of a plurality of metal layers 120, 140, 160 which are stacked and interconnected by vias 130, 150. A passivation layer 180 is formed on the top metal layer 160 and is etched to expose a bond pad window 170. Such a bond pad structure is widely used because of its employment of a great number of layers of metal and its convenience in connecting the layers. However, due to package stress and potential damaging forces, devices are not allowed to be disposed under this bond pad structure, namely the space between the bottom of the bond pad structure and the silicon substrate 100 must be designed as a device-prohibited region 110. For this reason, an area must be specially provided for the bond pad structure on a chip, which is disadvantageous for the reduction of chip areas.